1. Field of the Invention
This invention relates to integrated circuit technology and more particularly to capacitive integrated circuit elements and their use in bipolar integrated circuit applications.
2. Description of the Prior Art
In the design of digital systems it is often found that two different integrated circuit technologies, such as bipolar and field effect, are required to obtain overall system performance objectives. For example, it is well known to utilize bipolar circuitry for logic and clock driving applications and field effect circuitry for memory applications. Since bipolar circuitry normally operates at voltages considerably less than required for operating field effect circuitry buffer circuits are required to boost bipolar signal levels to field effect levels. Specific implementations usually use bipolar circuitry to provide the buffer function.
Because field effect circuitry is particularly prone to provide voltage drops of one threshold voltage (typically 0.5 to 1.5 volts) per logic stage, it is important that field effect input signals be as close as possible to the drain supply potential of the field effect circuits used (typically 8 to 15 volts). Emitter follower circuits are used almost exclusively, and to eliminate or reduce the base/emitter drop inherent in such circuits, some form of capacitive charge retention or bootstrapping element is used. For example, U.S. Pat. No. 3,656,004 to Kemerer et al, entitled "Bipolar Capacitor Driver," utilizes the built-in base/emitter capacitance itself to provide additional stored charge to maintain the output emitter follower device conductive for a sufficient time after the base driver circuit becomes non-conductive so that the output voltage approaches the supply potential. The article "Bipolar Bootstrap Circuit," by H. Schettler, IBM Technical Disclosure Bulletin, February 1976, pages 2818-2819, teaches a similar charge storage technique in which the base/collector capacitance of a bipolar transistor is used to provide additional current to sustain the driver device conductive after its driving source has been turned off. In both examples, the amount of charge capable of being retained is limited by large parasitic capacitances from device elements to the integrated circuit substrate and by the time required to charge the internal capacitances after the output begins to rise.
The article, "Dynamic MOSFET Shift Register Array Clock Driver," by E. Seewann, IBM Technical Disclosure Bulletin, February 1974, pages 2767-2768 and U.S. Pat. No. 4,002,931 to Tsang et al, entitled "Integrated Circuit Bipolar Bootstrap Driver," utilize a bootstrap capacitance coupled from the emitter follower output to its input to provide a boosted voltage level to maintain the output device conductive after the input to the driver would ordinarily cease. FIG. 1 illustrates a simplified driver of the bootstrap type in which an input signal is applied to T1 and an inverted output signal Vout produced at voltage node A. When Vin is a high level logic signal T1 conducts causing T4 to conduct discharging node A to ground. When T1 is conducting, the base of T2 is near ground and T2 is off. The voltage drop across R1 enables feedback capacitor Cfb to charge to approximately VL minus the Vbe of diode D1. When the input changes from its high to its low logic state, T1 and T4 are turned off. The base of T2 begins to rise causing T2 to turn on and, in turn, T3 begins to conduct allowing the output Vout to rise. The rate at which node A rises is determined by the size of the capacitive load (not shown) being driven, the size of Cfb and the size of various parasitic capacitances, shown as lumped variable capacitance Cp. The larger Cp becomes, the larger Cfb must be to provide sufficient feedback to node B to supply current to the base of T2 to sustain its conduction until node A reaches the drain supply potential VH. In many instances, Cfb is too large to be included on the same substrate as the remainder of the circuit and is provided as a discrete external component. The above mentioned Tsang et al patent describes an integrated thin oxide capacitor as shown in FIG. 2. As shown, the output, node A, is ohmically connected to an N+ doped semiconductor region with the P+ isolated pocket formed in the N type epitaxial layer grown on a P- substrate. Note that although the capacitance Cfb between contacts A and B is constant, the capacitance between contact A and the substrate comprises a reverse biased p-n junction 8. FIG. 3A is a schematic representation of the capacitor shown in FIG. 2 while FIG. 3B is a representation of the capacitive effects of the capacitor when node A is rising. The reverse biased diode characteristics correspond to a variable capacitor Cp in which capacitance decreases as node A rises. Because the ratio of Cfb to Cp may be small, the efficiency of the feedback effect may be reduced. Although other capacitive structures, such as junction capacitors, see for example U.S. Pat. No. 3,474,309 to Stehlin, may be suggested, these too have very large parasitic capacitances coupled to the capacitor terminals which decrease the efficiency of the circuit.
Additional references which may be considered pertinent include: U.S. Pat. No. 3,641,368 to Gamble et al which illustrates the use of an NPN transistor having a shorted collector-emitter to form a circuit capacitance and U.S. Pat. No. 3,678,348 to Reber et al which shows a multi-emitter bipolar transistor having a plurality of contacts commonly coupled to a single emitter electrode and a separate multiple contact base electrode.